FIG. 1 shows a differential driver 1 that takes a differential input on conductors 2 and 3 and converts that input into a serial data stream on an output conductor 4.
It is known to use the differential driver 1 of FIG. 1 as an input stage to a digital system. It is also known to generate a clock signal for the digital system from the data stream on the output 4 of the differential driver 1.
FIG. 2 shows a single data stream and an associated clock signal. The clock signal shown in FIG. 2 samples the data on both the rising and falling clock edges and the clock transitions are closely aligned with the mid-point of data transitions. Such alignment is preferable as the data is given the maximum time both before and after the clock transition in which to be stable. This gives the best chance of the set-up and hold times of subsequent circuits not being violated.
One method of achieving such clock alignment uses the circuit of FIG. 3. A phase locked loop (PLL) 5 is shown with an input 7 receiving a reference clock signal at the required frequency. The PLL generates a number of clock outputs 8 (8 in the example of FIG. 3) each at a difference phase (spaced apart by 45 degrees in the example of FIG. 3). The clock signal can be placed close to the mid-point of the data transitions by selecting the most appropriate clock signal from the output 8 of the PLL 7.
Another method of determining the optimum clock signal is demonstrated with reference to FIGS. 4 and 5. FIG. 4 shows a phase wheel with 8 phase signals indicated, representing the eight phases of the PLL output 8. Those phase signals are plotted at 0, 45, 90, 135, 180, 225, 270 and 315 degrees respectively. The phase of a data stream relative to a reference signal (for example, relative to the reference clock input) can be plotted on the phase wheel. Once the phase of the data stream is “plotted” on the wheel, the outputs 8 of the PLL that are located either side of the data stream can be identified.
FIG. 5 is a block diagram of a circuit for generating the appropriate clock signal. The output of the differential driver 1 is passed to a phase detector 9 that determines the phase of the data (for example, with reference to the generated clock signal). The output of the phase detector 9 is passed to a phase interpolator 10 along with the eight clock signals from the PLL 7. A clock signal is generated by identifying the two phase signals from the PLL 5 between which the phase of the data stream falls and using the phase interpolator to generate a clock signal with a phase between those two clock signals. In the example of FIG. 5, the output of phase interpolator 10 is fed back to an input of the phase detector 9. The phase detector 9 is thus used to determine the difference in the phase at the output of the phase interpolator and the phase of the data stream in the data channel. A typical phase interpolator may generate the most appropriate clock phase between those phase inputs from 16 possibilities. Thus the phase wheel can be divided into 16×8 (i.e. 128) clock phases.
The purpose of generating a local clock signal for each data channel is to ensure that each clock signal is optimised for that channel. This is particularly significant when the relative delays in the channels are not constant. Such a system is used, for example, when it is not acceptable to simply select a single clock and to use that for all data channels.
Thus in a system where each data channel is likely to have a different phase, the generation of a local clock for each data channel is advantageous. This requires the phase of the data for each channel to be identified. The more frequently the data signal of any given channel changes (i.e. has edges), the more accurately the relative phase of the data in that channel can be determined. The inventors have noted, however, that if the data signal is static (i.e. there are no data transitions for a significant period of time) then it is not possible to determine the phase of that data channel. One option for handling such a situation is to retain the previous phase value until another data transition occurs. However, this suffers from the disadvantage that actual phase of the data in the channel can become significantly different to the phase value of the local clock.